ASIC design based on single-chip CMOS speech synthesis
introduction This article refers to the address: http:// In recent years, voice ICs have developed rapidly, and the scope of them has become wider and wider. Vending machines, ATM teller machines, direct telephones, and toys should be used to synthesize speech synthesis chips. The chip is pulse-width modulated, and the digital signal is reduced to an analog signal, so that the circuit output does not need to be connected to D/A conversion; at the same time, the chip can be realized in the form of a pure digital circuit, so that the voice synthesis circuit is conveniently integrated. The circuit (ASIC), in order to improve the anti-interference ability of the circuit, increases the stability of the system, and at the same time reduces the production cost and simplifies the board-level circuit complexity. 1, speech synthesis chip structure The speech synthesis chip first stores the voice data into the ROM in LOGPCM coding mode, and the total length of the voice is 35 seconds. The voice is divided into 4 voice segments and 2 trigger buttons to determine the trigger mode of the chip according to different requirements, and each voice segment is specified to play differently. Speed, set the "voice group skip function" to play the current voice segment (S1), then play the specified voice segment, and set the specified voice group to progress infinitely. The same two trigger keys select the input or output, the audio output PWM1PWM2 two outputs, directly drive the speaker; the frequency oscillator has two options: the part of the adjustable frequency oscillator part frequency oscillator. The overall design block diagram of the chip is shown in Figure 1. 2, the voice synthesis chip works The speech synthesis chip has two control signal terminals: IO1IO2, which has four segments of voice capacity. According to the design, the IO2 priority level is IO1, and different voice segment speech signals are played through different inputs, and the two control signals IO1IO2 trigger modes are triggered by edges. The voice has no re-trigger (segment cover segment) function, and each time the output segment of the output segment has a voice capacity, the segments are sequentially outputted with various segments of speech. The chip works, IO2 starts to trigger the first speech (S1), if IO2 level, IO1 trigger is invalid; when IO2 level, IO1 triggers the most speech (S4), if IO2 continues to trigger, cycle output Each paragraph of voice. 3.1 timing generation circuit This part of the circuit provides a clock signal to the entire speech synthesis chip, and the speech synthesis chip only includes a clock to play the speed. The chip stores 8 bits of voice information in LOGPCM encoding mode, and adopts PWM to modulate. It needs at least 28 times PWM data read frequency to modulate, so that the PWM signal output duty cycle can achieve 256 levels. The speech signal is sampled at 8KHz, so it is modulated at a clock frequency of 8K×256=2M, so that the chip is frequently played. ASIC design, up to 2MHz clock frequency, loop oscillator, three CMOS inverters, one capacitor chip resistor, adjust the chip resistor to generate different frequency oscillation signals, so to achieve different playback speed by changing the resistance value . At the same time, the chip section two-way circuit is connected in series to achieve 28 division. 3.2 input signal control module circuit Input signal control module input signal IO1IO2ROM address for end control, determine the playback voice segment, the chip design ROM has 16 addresses, 8 data lines, voice is divided into four segments, each segment of voice occupies 4000H address units, the first segment of voice storage The address range is from 0 to 3FFFH, the second segment of voice storage address ranges from 4000H to 7FFFH, the third segment of voice storage address ranges from 8000H to BFFFH, and the fourth segment of voice storage address ranges from C000H to FFFFH. The circuit design avoids some state misoperations, so the input signals IO2 and IO1 perform two-stage registration, firstly detect the IO2 rising edge, and when the IO2 rising edge, the signal output port first outputs the "00" signal (signal output terminal level module: address Output module signal control input); so that each detection IO2 liter edge, let a 2-bit counter increase by 1, IO2 through the register, detect the rising edge again, signal output "01" signal. Then start the address output module, when IO1 rising edge, first judge IO2 no level, only IO2 level state, IO1 can be activated, working mode IO2; otherwise IO1 is invalid. The circuit schematic is shown in Figure 2. 3.3 ROM address output module The ROM address output module receives the stage input signal control module control signal, outputs different address signals to read ROM data according to different control signals, and the ROM has 16 address lines. Therefore, the ROM address output module designs a 16-bit addition counter, first designing a 2-bit addition. The counter is further composed of two 2-bit addition counters to form a four-bit addition counter, and the three four-bit addition counters constitute a 12-bit addition counter, and the maximum of 12-bit addition counters and 2-bit addition counters constitute a 14-bit addition counter, 14 The bit addition counter can just count 3FFFH from 0, and the segment of the first voice storage address range, the starting address of each segment of speech storage is equivalent to 3FFFH corresponding multiplier plus 1, so multiply, its calculation: DOUT=C+MUL×(D+ 1), its DOUT represents the output ROM address; C represents the 14-bit addition counter; MUL indicates that the speech segment number is played minus 1; the D constant is 3FFFH. The circuit schematic is shown in Figure 3. 3.4 Pulse Width Modulation (PWM) Module The module stores ROM data for decoding, and the decoded audio signal is directly output by the horn, which is: modulating the duration of the pulse carrier of each instantaneous value of the continuous modulation signal. The digital signal is actually converted into an analog signal, which restores the sound [2]. The modulated pulse signal width is dependent on the instantaneous value of the modulated signal. When the pulse amplitude is constant, the modulated signal is completely represented by the pulse width, and the signal is transmitted, so that the signal amplitude distortion interference is solved, and the limit is eliminated. Since the sampling frequency of the speech signal is 8 kHz, the output signal has a duty ratio of 256, and the 8-bit counter realizes 0256 counting, so that the output signal "1" time maintains the corresponding data length. The data read-in system modulation clock (2MHz) falling edge temporarily starts to operate, and when the 8-bit counter "0", the data is read. Therefore, the PWM modulation is completed, and the modulation period has not started the time slot. Only the time slot starts to read the data to affect the PWM modulation [3]. The most read data is compared when the 8-bit counter count value is compared. If the count value is when the data value is read, port 1 (PWM1) outputs the level "1", otherwise the output level is "0", so that the output signal is occupied. It occurs more than the input LOGPCM data, thereby implementing the voice output function. The circuit schematic is shown in Figure 4. 3.5 Storage Voice ROM The ROM (Read Only Memory) is composed of an address decoder and a storage matrix output buffer. The address decoder ROM inputs 16-bit address codes A0, A1, ..., A15, and outputs an output signal W0, W1, ..., W65535. Word line. Each word line output should have a storage unit address, such as W0 should be 0 unit address, W1 should be 1 unit address. This address selects the specified unit from the memory matrix and its data is sent to the output. The storage matrix is ​​composed of a basic storage unit, and includes a quantity storage unit. The storage unit ASIC is composed of a MOS tube, and is composed of an input strip word line for outputting eight bit lines (D0 to D7). Each word line bit line intersection has a storage unit, and the storage bit has a binary value of 0 or 1. Each or group of memory locations should have an address [4]. 4 function simulation and analysis From the perspective of actual cost, the 0.5um silicon gate process is developed for the flow film. According to the nMOS tube width to length ratio of 14:1, the pMOS tube width to length ratio is set to 14:1 ratio (some places need to be properly adjusted), and each module is used. Connection, QuartusII function simulation, simulation of the waveform as shown in Figure 5: its clk_div256 frequency divider circuit output signal, the final output of the 2 channels of audio signals PWM1, PWM2, flag0 voice playback flag signal, flag1 when the voice signal is played Ping, play interrupts the “0†signal, D[7..0] stores the voice data stored in the ROM, IO1 “1†immediately plays the most segmented voice signal, when IO2 “1â€, it plays the third to the third Segment speech; sig[1..0] speech segment, "1" indicates that a certain segment of the third segment is played, and when "2", the most segmented speech is played, and IO2 is sequentially played to the third segment of speech. Multiply, when there is the first IO2 "1", the multiplication mul[1..0] outputs "0", and so on. When there is a fourth IO2 "1", mul[1..0 ] Cleared again. 5 Conclusion This paper makes innovations: In this paper, we study the optimization method of speech synthesis chip, and design the speech synthesis chip circuit more simplified, and the performance is more stable. At the same time, pulse width modulation (PWM) speech signal modulation and demodulation behavior is demonstrated, and the FPGA hard verification method proves that the PWM technology realizes the all-digital speech synthesis output line, so that the speech synthesis chip is realized in full digital form.
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3. Speech synthesis chip design