USB 3.2 Device and Host Based on HAPS-80 FPGA Hardware Prototyping Platform
The USB 3.1 Gen.2 interface has been widely used. The high bandwidth of 10 Gbps (1.25 GB/s) is quite abundant, but there is no limit to the technical progress. The new generation USB 3.2 standard specification was officially announced at the end of September 2017, and Synopsys (new (Science and Technology) is now demonstrating USB 3.2 for the first time. The USB 3.2 device and host of this demonstration are based on the HAPS-80 FPGA hardware prototype platform. The USB PHY physical layer is manufactured using the FinFET process. The bandwidth of each channel is 10Gbps, and the dual channel strength reaches the required 20Gbps (2.5GB/s). USB 3.1 Gen.2 has doubled. The HAPS platform is connected to a Linux PC through the PCI-E bus. The device is configured as a mass storage device, such as a USB 3.2 SSD, a USB 3.2 U disk, and a small amount of RAM on the FPGA is used as memory in order to reduce the delay. The host platform is similar, and is affixed to a PHY motherboard. The HAPS connects to the Windows PC through the PCI-E data cable. The FPGA motherboard is connected to the PC as a USB 3.2 xHCI host expansion card. The system uses a standard Windows driver. The speed of the demonstration was 1.6GB/s, which is only about 2/3 of the power compared to the standard limit. There is still great potential to be tapped. In addition, the USB 3.2 era interface style will be unified as a more convenient, more flexible, more powerful Type-C. Type-A that has been circulating for many years will gradually be withdrawn from the historical stage. However, as with every previous standard upgrade, the popularity of USB 3.2 still takes a long time, and it is expected that relevant devices will be available next year. In addition, Intel and AMD have only recently supported USB 3.1 Gen.2, and the platform has integrated USB 3.2. Far away, it is still the third-party master chip in the initial stage.
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