What is the task of fpga/asic design entry digital circuit design?

First of all, you need to know what you are doing? The digital circuit (fpga/asic) design is the implementation of the logic circuit, so the statement is too narrow, because asic is still a lot of simulation, huh, huh. We only discuss digital circuit design here. In fact, how to use the schematics we learned from the classroom (very few people use this pull), or hardware description language (Verilog / VHDL) to achieve, perhaps you think this is too simple, in fact, complex design That is to use the logic gate circuit. When you learn the logic circuit, you may be confused about the Karatu, the trigger state to push the formula down, but in fact, one thing you can rest assured is that the actual design only requires you to understand the interface timing and function, you don't need to be so complicated. To overthrow the formula, as long as you can express the logical relationship clearly by language, the specific logic relationship is used in the circuit, you can not care, the synthesis tool can help you deal with it. Of course, you need to know the functions of the basic gate circuit, such as D flip-flops, functions such as gates, NOT gates, or gates (not to mention much, the two inputs are relatively simple). --- In a word, using verilog or VHDL to describe the logic function of the design object, this is the task of digital circuit design!

Speaking of this entry must have two basic skills: logic circuit foundation, hardware description language. With these two basic skills, even if you can't find a job, hehe, maybe you will say, now you have to ask fpga for an interview. Is it so simple to ask timing analysis? In fact, after you have these two basic skills, you can learn slowly. Note that the learning of hardware description languages ​​and logic circuits can be learned synchronously, and it is important to remember that learning hardware description language progress depends on your understanding of the circuit and your use of the simulator. Why do you say this? Because the hardware description language RTL (register transfer level) is mainly used to integrate the synthesis tools into circuits, so to meet the specific coding style, these coding styles will correspond to this specific logic, such as how to write sequential circuits, how to combine circuits Write, this is a certain constraint, if you are familiar with the logic circuit, you know what kind of gate circuit will be used after the code is generally integrated; in addition, the code must be simulated, which is unavoidable. --- No simulation, how do you know that the code you write meets the design requirements? Being able to use the emulator skillfully, you have the basic ability to debug your code. Otherwise, writing more code is useless. This is also a factor that I am excited about today. I am currently using the vera verification language, using the C++-like style. For the custom verilog, I am not used to the high-level debugging environment. It takes a day to locate a problem; but once you can Skilled in using the compile simulation tool, you will find that many of your own ideas can be quickly written into code and debugged to improve your understanding of the language. The progress of learning is to implement your own ideas in words and to verify that the verification is correct.

Learning fpga should start with xilinx and altera devices. This is the world's two largest programmable device suppliers. Of course, learning fpga should have a certain Verilog basis. Let's use xilinx as an example to explain.

Fpga's development process, first of all, synthesis, place and route, generate bit files, and finally download.

Comprehensive, you can use synplify, you can also use synpsys's fpga compiler, of course, you can also use ISE's own comprehensive tools, Mentor also provides fpga development tools. As an introduction, synplify is a good choice. First, you can familiarize yourself with the circuit structure. Second, as an introduction, you can check the quality of your code in the synplify integrated process. When I didn't use QA to do code QA, I used Synplify as a QA tool. Of course, you have to be familiar with Synplify's comprehensive strategy and comprehensive report. After the integration is completed, an EDIF file is generated.

As xilinx, third-party integrated tools can provide EDIF or NCF files. The XST synthesis tool comes with NGC output. At the same time, we may also use xilinx core, core files mainly exist in edn form; We will enter the implementaTIon stage. This stage is divided into three parts: translate, Map, and PAR. The translate is to convert the netlist file of the netlist and core into NGD files. As the input of Map, Map maps the netlist files. To the basic components in Xilinx, such as slice, blockram, etc., the last PAR is place and route, and finally you can generate bit files. Recommended book "FPGA / CPLD design tool - Xilinx ISE5.x detailed use", the book has a detailed description of the entire design process, but also introduced a lot of advanced skills, but for asic designers, unless you want to do FPGA verification, otherwise There is no need to look at these things, because learning FPGA is a complete ASIC design process. Unlike ASICs, designers also divide front-end and back-end. FPGAs involve many factors, including internal structure and board-level debugging. .

In addition to learning the development process, fpga learns its internal structure. The structure of xilinx fpga is as follows: the basic unit is LUT, SLICE is composed of LUT, CLB is composed of SLICE, and how many LUTs form SLICE, and how many SLICEs are composed of different device types, you can refer to datasheet. In addition, it is Block Ram, DLL or DCM, and DSP. Now popular SOC, many high-end devices are also embedded in the microprocessor, there are soft cores and hard cores. The best introductory book for learning the hardware structure is the book of Mr. Meng Xianyuan. Although the time is a long time, from the book I read, only he is the most thorough analysis. Now I have introduced more books in this area. However, I have to remind you of what device to use to see what device's datasheet. It is not necessary to use this thing as a textbook. Check it out.

Learning fpga has a chance to buy a board and write a program to run it. It should be a very good thing. Now many fpga designs for broadband communication applications have Serdes interface, DDR interface and the like, which are not special requirements. It is estimated that it is not so complicated to write. It is possible to write several state machines or UARTs.

Last time we discussed ways to learn logic and hardware description languages. How to buy a book, how to read a book. This time we discuss the difference between fpga and asic design.

Fpga field programmable devices, PLD aspects, compiled into a configuration file by verilog, loaded into fpga to achieve specific functions. In fact, fpga itself is a chip, but you can modify the internal logic connection and configuration to achieve the functions you want by programming.

The asic-specific integrated chip is a chip designed for a specific application. To achieve asic, just like starting with a blank sheet of paper, you have to have the code, then synthesize, then layout, routing, get GDSII and then go to the stream. Fpga device is also through this process, but he should be considered a general-purpose device, such as cpu, can be applied in many cases, unlike mp3 chip, it can only play mp3, so it can only be called a dedicated chip. Regardless of whether it is general or proprietary, there is a similar process. Note that the above is the flow of a semi-custom digital integrated chip. As a simulation, there are some special full-custom chips, usually starting from the layout.

Speed: The same process and design, the speed on fpga should be slower than asic. why? Because fpga is based on a general structure, that is, LUT (look up table), it can implement adder, combinatorial logic, etc., and asic, generally your adder is the adder, and the comparator is the comparator, fpga structure The versatility inevitably leads to redundancy; in addition, as the basic unit of fpga is LUT (LUT constitutes SLICE, SLICE constitutes CLB--this is the structure of xilinx), for this large design, if a LUT cannot be implemented, two LUTs must be used. A SLICE can't be realized with CLB. Different structures are in a specific position, and the interconnection between signals causes the wire delay to be a non-negligible part. There is no structural limitation for asic, and it can be spatially close to a specific reality. In contrast, wire delay and cell delay should be smaller than fpga. Of course, there are also DFFs in the LUT. As a high-speed design, you usually take a shot after a simple combinatorial logic operation, and then do the next step.

Area: From the above, fpga is still much larger than asic. If you know that your mobile phone baseband chip is made by an fpga, you will definitely be mad. n big fpga, I think it is still difficult to put it in your pocket.

Power consumption: It is also obvious that fpga power consumption is larger than asic.

All of the above are based on the same manufacturing process and design conditions. From another perspective, that is, development speed and process, fpga development is simple, asic development process is long-term risk.

In addition to the code, fpga generates configuration files from synthesis to place and route, which are automatically generated by software. Of course, there are certain constraints. However, you have to know that you are only painting in a house, this house is ready-made fpga. If you are not satisfied with the painting, you will get rid of it and draw one more. It won't affect the house - as long as you don't burn fpga.

Asic design, you not only have to care about the code, but you also care about timing, care about the design to meet DFT requirements, care about layout, care about SI. . . . . . It's the equivalent of nothing. Now the house is going to be covered by you, the floorplan, how to cover it, how to go the power line, how to design the water pipe, what the door opens in that direction, and so on. Once the house is covered, do you feel dissatisfied? You have to take it down, and a flaw affects the house. You want to paint, you can, you have to paint well, if you don't paint well, you can't change it. Because asic is not a programmable fpga, the internal structure is determined once it has been streamed. Bugs are deadly things in asic!

For the cost, fpga is expensive in a single piece, and the development tools and risks are basically non-existent. For the cost and development tools of asic expensive, the NRE cost becomes quite expensive with the improvement of the process. Unless your chip can be mass-produced once successfully, the cost per piece will be extremely expensive! You think about leaving a film 50W and getting you back 100 samples, all bugs. How much is it? ? ! !

Development cycle, fpga6 months, asic one year. If a designer says that he tapped 4-5 films within a year, it is estimated that he is only doing synthesis or backend. From design to verification, it is a long time. Once the verification is completed, the process of RTL2GDSII is very fast.

Asic design entry (front end)

How is the front and back of the asic design divided? The front and back ends of the asic design are like the differentiation of the ImplementaTIon before and after the FPGA design (Xilinx). The front end is responsible for all the things before the netlist, and the back end is responsible for the Netlist to GDSII process. Note that this is not absolute. Now the front end can also do some back-end things (physical synthesis) with Physical Compiler. With the 殴ひ盏 (17)    蠖 蠖 姆 姆 侥 侥 侥 侥 侥 侥 侥 侥 侥 侥 侥 侥 侥 侥 侥 侥 侥 侥 侥The front end of SIC also considers a lot of factors about Power, DFT, etc.; the back end, here is a rough introduction, Floorplan, layout planning, mainly refers to Macro placement and PG ring planning; Place-layout, mainly refers to The placement of the standard cell; Route, wiring; it also involves DFT, DRC, LVS and STA. These things can be understood.

The introduction of ASIC front-end design, this process fortunately did not forget. Unlike FPGAs (which have too many relationships with devices), the digital front end should be the same.

1 System Planning Requirements Analysis----SpecificaTIon

2 Module division ----- According to the SecureaTIon, start dividing the module, specifically to the interface timing and function, and finally write the detailed design document.

3 module code input ---- pay attention to Coding Style

4 module-level simulation verification --- line coverage should reach 99% (default statement is not covered)

5 System Integration and System Simulation Verification----The verification platform should be performed in parallel with the code writing after the specification is determined.

6 Synthesis----Get the netlist

7 STA-----Verify timing

8 Formal Verification - Verifying the Equivalence of Netlists and RTL

If Netlist2GDSII is the case, it should be fine. Estimated back-end personnel like DFT can help you. It seems quite simple, in fact, the most time spent in the front, that is, the integration of the previous steps is the most time-consuming, including the development of the specification, the module-level detailed design and verification, once you get a goden RTL, from RTL to GDSII is very fast. The so-called garbage in garbage out, the step after the synthesis is basically not a modification of the function, but according to the implementation of a specific function, so a good RTL is very important.

In terms of system planning, reset, clock scheme is the most important factor, followed by DFT; in the module encoding, it is necessary to pay attention to these requirements, such as not internally generating clock and reset signals, preventing unnecessary latches and so on. Module-level verification should be a key part of system verification. When we were doing TDSCDMA mobile terminal chips, Viterbi verified that it was composed of several steps. The verification at the module level was very perfect. Later, the system verified that the FPGA verified the last tapout. No problem. Of course, everyone cares about how to deal with it, how to deal with STA, how to achieve formal verification, because these steps are not accessible to everyone, after all, these tools are expensive; a company can easily find a few people to develop FPGA together, but Said to casually find a few people to do ASIC, it is estimated that the cost of the Tool will be rid of hundreds of W - here refers to commercial software, if you say that the D version can also be used, ^ _ ^ then you use it, The cost of streaming is also quite a lot.

Below I will introduce you to the various parts of the asic front-end design.

Before I introduce the process after the integration, I will introduce the process from system planning to pre-synthesis. The FPGA and ASIC here are not much introduced in this aspect. I have made up here and hope to help everyone. System planning is of course developed by system personnel. If you want to know how to make it, it is basically system function, performance, system interface, system clock scheme, reset scheme, DFT scheme; how much memory is used in the system, whether to use DSP, MCU, What is the architecture, the final die size and power is about, etc.; as a designer, most of you will be assigned to a module design. In general, after the system plan is developed, the module is divided. In many cases, it is divided according to functions. After the module is divided, the designer will continuously discuss the implementation solution and the solution to the key problem. The interface between the modules starts with the implementation scheme and timing of the module. After detailed discussion, these should be written into detailed design schemes. . Three years ago, my first design was to draw a few drawings and design. A small one, no documents, no sketches, and a month; after accumulating experience, the development process was changed. The method adopted by the company first writes the detailed design plan and then writes the code; you will find that it may take a month for the detailed plan, and the code can be written for half a month. Because the idea is clear, writing the code is of course simple. Don't write the code while writing the design plan. At the end, the problem is not solved. The code is changed and can't be used.

Then there is debugging. Now many companies write code on the server, and the network connection speed is very slow, not to mention debugging. My original habit, and now the habit is to design in this machine, the first writing is fast, the second simulation is fast, for the module design should be designed to debug a module after designing a module, instead of testing the module when the system is integrated. . So the speed of simulation debugging is very important, and using VCS to debug small modules on the server is not as good as using Modelsim on this machine. I just entered the new company and did the simulation design. I used the design to be completed in a month. I used it for two weeks. The reason is very simple. I have a platform for writing and debugging code. I can debug a code n times in ten minutes. Of course, this environment is not for everyone, it will be used, this is what I have accumulated in three years ^_^

Comprehensive tool

Section 1: What is synthesis? Synthesis, Taiwan translation for - synthesis, its role is to transform the RTL level code of the hardware description language into a gate-level netlist. Of course, the integrated technology is now mature, and there is a behavioral synthesis and physical integration. What we are discussing here is logic synthesis.

Integrated technology is an important technology to improve design productivity. Without the development of integrated technology, we can't use HDL to realize circuit design, because HDL is used for circuit simulation modeling, and later it is part of it. The subset is a synthesizable language, which is the RTL CODE we use. Many people get started with HDL design, thinking that HDL is only used for design, and did not see the initial side of HDL, so when verifying, you can't use other powerful features of HDL. If you have time, you can take a look at the Writing Testbench book to enhance your understanding of the role of the HDL language in verification. It is also a good complement to raising awareness of HDL.

We use the DesignCompiler as an example to explain the integrated process.

First of all, the comprehensive must use the comprehensive library, you can ask the manufacturer, the integrated library can be converted into a .db comprehensive library through the .lib library file, this process can be implemented in the DesignCompiler, what is in the integrated library? ? .db is unreadable, .lib is readable, it has the basic parameters of the library, the library running conditions, various parameters, the most important are two parts, one is WLM-Wire Load Model, one Gate The definition (input and output, function, timing parameters, area, etc.); this is just the library of StandarCell, in addition to other libraries, such as RAM, DSP's comprehensive library, all exist in the form of .db.

The synthesis requires three inputs, one is the code, one is the comprehensive library, and the other is the integrated script. The integrated script mainly includes the following contents, configuration of the integrated tool environment, operation condiction of the integrated object external environment, setting of WLD, constraints on the timing of the integrated object, comprehensive strategy, comprehensive optimization, comprehensive report and output. . Here's a ready-made script example for the person getting started. (tcl script)

####### Set Directary #########

Set LIB typical

Set SYNDIR $HOME

Set SRCDIR $HOME/src

Set SCRDIR $HOME/script

Set RPTDIR $HOME/rpt

Set SYNDB $HOME/db

Set SYNOPSYS "/cad/synopsys/"

######Enviroment############

Define_design_lib WORK -path $SYNDIR/WORK

Set bus_naming_style %s_%d

Set verilogout_single_bit "false"

Set hdlin_enable_vpp "true"

Set hdlin_enable_vpp "true"

Set verilogout_no_tri "true"

Set write_name_nets_same_as_ports "true"

Set compile_preserve_sync_resets "true"

Set ultra_optimization true

Set verilogout_equation false

Set verilogout_no_tri true

Set sdc_write_unambiguous_names false

######Libary#################

Set synopsys_path "$SYNOPSYS/libraries/syn \\

$SYNOPSYS/dw/sim_ver"

Set standarcell_path "*"

Set search_path "$search_path \\

$synopsys_path \\

$standarcell_path"

Set target_library "typical.db"

Set symbol_library "*"

Set synthetic_library "dw_foundation.sldb"

Set link_library "* $target_library dw_foundation.sldb"

######Read Design#############

Analyze -format verilog -lib WORK [list *] 》 $RPTDIR/analyze.rpt

Elaborate designtop -lib WORK -gate_clock 》 $RPTDIR/elaborate.rpt

Write -format db -hier -modified -output $SYNDB/$TOPMODULE.rtl.db

Current_design $TOPMODULE

#######Set INTERFACE ENV#########

Set_drive 10 [all_inputs]

Set_fanout_load 10 [all_outputs]

######Timing Exceptions#######

Set_false_path -from rst_

Uniquify

Link

########Set Clock#############

Create_clock -name CLK -p $PERIOD [get_ports clk] -waveform {0, 5}

Set_clock_uncertainty 0.3 CLK

Set_input_delay 3 -clock CLK [all_inputs]

Set_output_delay 3 -clock CLK [all_outputs]

Set_dont_touch clk

#######Compile Option############

Compile -map_effort medium 》 $RPTDIR/compile.rpt

#################################################

Report_timing 》 $RPTDIR/report_timing.rpt

Report_area ” $RPTDIR/area.rpt

#################################################

Write -format db -hier -o $SYNDB/*.db

Write -format verilog -hier -o $SYNDB/*.v

Write_sdf -version 2.1 $SRCDIR/. . /netlist/*.sdf

Write_constraints -cover_design -format sdf-v2.1 -output *.syn.sdf

Write_script -hier -out $SCRDIR/*.sdc

This is a very complete script structure (for reference only, this is just an architecture, the specific syntax may need to be supplemented and revised, not used in R&D, you have to spend a lot of time debugging scripts), used in the synthesis of RTL2Netlist Of course, the synthesis after PAR is definitely not written like this, and the reason is recommended to take a look at "advance chip synthesis". I will give detailed insights on each part of the script in the future, and I will write it here today. Hey, I wrote so much, that is, no one is willing to join! ^_^

############################################################################ ############################################################################ ####################

The comprehensive technology research can be traced back to the 1960s. The TJ Watson Research Center of IBM developed the ALERT system to transform the register transfer level algorithm description into a logical level structure. In the 1970s, the integrated technology developed rapidly, but mainly focused on Low-level logic synthesis and layout synthesis; in the mid-1980s, the widespread application of ASICs required large-scale, high-performance, short-cycle design of the chip, which greatly promoted the conversion from algorithm-level design to register transfer-level design description. High-level integrated technology.

Logical synthesis concept

The logic synthesis is responsible for translating the structural description of the register transfer stage into a structural description of the logical layer and transforming the structural description of the logical layer into a structural description of the circuit. Among the EDA synthesis tools commonly used in the field of digital IC design, the most authoritative is the comprehensive tool provided by Synopsys. Synopsys' Design Compiler (DC) is the industry's most popular and powerful logic synthesis tool. Users only need to enter the HDL description and time constraints of the design specifications, and it is possible to obtain a more optimized gate-level integrated netlist. In addition, DC integrates a powerful static timing analysis engine and supports interworking with back-end place and route tools.

Logical integrated process

In a sense, synthesis is the process of transforming the designed HDL tracing into a gate-level netlist. The integrated tool DC provided by Synopsys divides the synthesis into three steps: synthesis=translation+mapping+optimization. Translation refers to the conversion of a designed HDL description into a logic circuit composed of GTECH library components; the GTECH library is a general-purpose, process-independent component library provided by Synopsys. Mapping refers to mapping GTECH library components to a specific semiconductor process library. The circuit netlist at this time contains the relevant process parameters. Optimization is a process of further optimizing the circuit netlist based on comprehensive constraints such as delay, area, and line load model set by the designer. From the perspective of the use of integrated tools, the integration includes comprehensive environment settings, comprehensive constraints, comprehensive optimization, integration and back-end processes.

Comprehensive constraints are used to set the goals of circuit synthesis, including design environment constraints, time constraints, and area constraints.

Design environment constraints refer to a set of attributes used to describe external conditions such as temperature, voltage, drive, and load during design. Basic environment settings include settings for working conditions, load models, system interface drivers, or fanout capabilities. These attribute constraints are necessary for circuit synthesis. If the user does not have a description of the display, the DC will use the default value when synthesizing.

Time constraints include defining clocks, defining time constraints for clock networks, and timing path time constraint settings, as well as time constraints for asynchronous designs. Understanding the calculation of delays is the key to defining the right time constraints. Synopsys supports several delay models: one is the CMOS general delay model, the other is the CMOS segmented linear delay model, and the third is the nonlinear look-up table delay model. For the deep submicron design, the first two models are not commonly used. The nonlinear delay model calculates the delay time value by taking the input transition time and the output capacitance load as parameters, and the results are listed in the form of tables for DC lookup.

The area constraint and the time constraint are a pair of contradictions and need to be compromised. The DC synthesis defaults to a time constraint with a higher priority than an area constraint. The area optimization is not performed by default when DC optimization. If you focus on the area of ​​the chip, you can use the set_max_area command to set the area constraint so that the DC continues to perform area optimization after completing the timing constraints.

After setting the comprehensive constraints, general optimization is not immediately performed. Because for a larger design, the integration time is very long. Therefore, it is necessary to confirm whether the comprehensive constraint command is correctly added to the design before synthesis, which can reduce the risk of re-synthesis optimization due to incorrect integrated constraints and reduce the time of comprehensive repetitive. The commands for checking the comprehensive constraint settings are report_design, report_port –verbose, report_clock [-skew], report_constraints, report_timimg_requirement, and so on.

Many layout tools only accept a comprehensive netlist in Verilog or EDIF format as input. After the integration, the Verilog format netlist is provided to the backend layout tool, and the IC engineer must also handle the integrated netlist:

1. Solve the problem of instantiating the same submodule multiple times

2. Fix the naming of some connections in the design to simplify the integrated netlist

3. Remove ports that are floating throughout the design

4. Ensure that the pins of each instantiated unit are visible

5. Avoid the definition of assign statements, transmission gates, and tri-state connections in the netlist

6. Avoid unnecessary gated clocks or gated reset signals in the netlist

7. Avoid the implementation logic of the instantiation name referenced in the netlist.

After the integration, we have to perform gate-level simulation on the integrated netlist. On the gate-level simulation, the VCS simulation tool provided by Synopsys runs faster on the server. One step in the gate-level simulation process is timing simulation with timing back-off. The SDF file is written by DC or PT, and the logic delay and line delay are back-inputted into the circuit in the netlist to simulate a more realistic situation.

Functional simulation and verification

The purpose of verification is to ensure that the functional characteristics provided by the design implementation are correct and consistent with the functional characteristics defined in the design specification. The purpose of verification is to prove that the design is error free. However, in fact, verification can only prove that some design errors exist or do not exist. Verification is a process that may exist in an exhaustive design. There are quite a few verification methods and verification strategies in the industry. The main verification methods can be roughly divided into functional simulation technology, static timing analysis technology, and formal verification technology.

Functional simulation and debugging

Functional simulation is the main form of design verification. From the abstraction level of simulation, including event based simulation, cycle based simulation, and transaction based transaction simulation.

The event-based simulator considers the change in input stimulus to be the trigger of the event. Each simulation time simulator processes an event trigger and recalculates the entire design based on the content of the event trigger until a simulated steady state occurs.

The event-triggered simulation feature covers both the functional and timing models of the design, and the simulation results are accurate. It is very easy to detect the glitch circuit in the design, especially for the simulation of asynchronous circuits.

The clock cycle-based simulation has no concept of time in one clock cycle. It only triggers on the rising or falling edge of the clock, and the time of each clock cycle is calculated once for the circuit.

Transaction-based simulations use data packets, graphics, speech, and other objects as direct stimulus excitations rather than excitation waveforms added to the design pins.

There are three main methods of functional verification: black box method, white box method and gray box method.

The architecture test environment is called "writing testbenches" in the software simulation process. Testbench usually refers to code that properly configures the design and produces a test stimulus that selectively responds to it. Testbench is generally implemented in the hardware description language Verilog HDL or VHDL, and can also include C or C++ language generated excitation data plus PLI. Now the industry also has the special verification languages ​​Vera and Specman E.

I will introduce Modelsim and VCS to you in the future:)

Static Timing Analysis (STA) stands for Static Timing Analysis, which provides an effective method for timing verification of large-scale gate-level circuits. It refers to the topology that requires a more circuit netlist, and can check the timing characteristics of all the paths in the circuit design. The coverage of the test circuit can theoretically reach 100%, thus ensuring the completeness of the timing verification; and because the test vector is not needed, Therefore, the time required for STA verification is much smaller than the gate level simulation time. However, static timing analysis also has its own weaknesses. It cannot verify the correctness of the circuit function. Therefore, this must be guaranteed by the functional simulation of the RTL level. The correctness of the gate-level netlist function can be implemented by gate-level simulation technology. The formal verification technique mentioned later. It is worth noting that static timing analysis can only effectively verify the correctness of the synchronization timing. For most of the design, the timing verification of the asynchronous circuit may be included in the gate-level simulation to ensure the correctness of the timing. From this we can draw the conclusion that static timing analysis and gate-level timing simulation are to analyze the circuit from different focuses to ensure that the timing of the circuit is correct, they are complementary.

Synopsys' Prime time timing analysis tool analyzes the design circuit as follows:

1. From the main input port to all the triggers in the circuit

2. From trigger to trigger

3. From the trigger to the main output port

4. From the main output port to the main output port

The static timing analysis tool breaks up the entire design circuit into the above four types of timing paths, analyzes the timing information of different paths, and obtains the calculation results of setup time and hold time. Of course, there are several other paths: such as gated clock, DFF reset terminal, please refer to the PrimeTime manual.

A good entry for STA is also a reload from 5life http://techcenter.dicder.com/data/2006/0114/article_102.htm

Formal verification is a static verification method. It judges whether two designs are functionally equivalent according to the circuit statically. It is often used to judge whether a design is consistent before and after modification. It does not require a test vector to run, but it must have a reference design and a design to be verified. Referring to the design, the designer believes that the functionally complete design can theoretically be implemented in a high-level language such as C, C++, or in the modeling of the integrated circuit é•…è©“ystemC, or the verification language vera or SpecmanE; In terms of implementation, the reference design in most formal verification processes is our RTL design, which is generally implemented in verilog or VHDL.

When the RTL-level functional simulation or FPGA verification is over, the traditional IC design flow needs to complete several door-level simulations: integrated back-door simulation; gate-level simulation after DFT; gate-level simulation after place and route, etc., if the design is large Or the circuit is very complicated, and often requires a large test vector to verify that the design's function and timing are correct. This makes the time spent in the gate-level simulation increase with the increase of the circuit scale.

Formal verification is like an iterative algorithm in the ASIC design flow. The initial input is the RTL design. For each comparison, the last compared design (n-1th) is used as the result of the reference design processing (nth time). For comparison, the reason for this is based on the following considerations:

1. Before the formal verification tool begins to compare, first find a one-to-one comparison point in the two designs.

2. If a design change is too large, the functions before and after the change are completely consistent, but if the formal verification tool cannot find a suitable comparison point, it will be considered that the two designs are not equivalent.

Formal verification is mainly used in the ASIC design flow in the following aspects: RTL-RTL comparison, RTL-GATE comparison, GATE-GATE comparison. Using formal verification to compare RTL and RTL, it can verify and ensure that no functional errors are introduced in the process of code modification in a short period of time; the comparison between RTL and GATE is to verify the source code and the integrated gate-level network.表是否等价，以保证综合过程中不会出现任何错误；进行GATE与GATE的对比，主要是发生在验证插入DFT后的电路网表在功能上是否一致；生成时钟树前后的电路网表在功能上是否一致；布局布线前后的电路网表在功能上是否一致等。

可测试性技术（Design For Testability-DFT）就是试图增加电路中信号的可控制性和可观测性，以便及时经济地测试芯片是否存在物理缺陷，使用户拿到良好的芯片。其中包括Ad Hoc技术和结构化设计技术。目前，任何高集成度IC设计系统都采用结构化设计技术，其中主要扫描技术和内建自测两种技术。一个电路的测试性问题应该包括两个方面：

1.由外部输入信号来控制电路中的各个节点的电平值，称为可控制性。

2.从外部输出端观测内部故障地难易程度，称为可观测性

扫描技术是指电路中的任一状态移进或移出的能力，其特点使测试数据的串行化。比较常使用的是全扫描技术和边界扫描技术。全扫描技术是将电路中的所有触发器用特殊设计的具有扫描功能的触发器代替，使其在测试时链接成一个或几个移位寄存器，这样，电路分成了可以进行分别测试的纯组合电路和移位寄存器，电路中的所有状态可以直接从原始输入和输出端得到控制和观察。这样子的电路将时序电路的测试生成简化成组合电路的测试生成，由于组合电路的测试生成算法目前已经比较完善，并且在测试自动化生成方面比时序电路的测试生成容易得多，因此大大降低了测试生成的难度。

对于存储器模块的测试一般由生产厂家提供专门的BIST电路，通过BIST电路可以方便地对存储单元地存取功能进行测试，所谓的BIST电路是指把测试电路做到IC里面，利用测试电路固有的能力自行执行一个测试存储器的程序。另外MBIST还可以解决RAM SHADOW的问题提高芯片的可测试性。

为什么要做DFT呢？因为我们的设计，也就是RTL到GDSII交出去的只是一个版图，最后芯片需要生产织造是在foundry做的，也就是厂家根据你提供的数据GDSII做成芯片。这个流程过程中可能出现缺陷，这个缺陷可能是物理存在的，也可能是设计当中的遗留问题导致的，另外一方面在封装的过程也可能出现缺陷。为了保证我们的芯片能够不存在物理上的缺陷，所以就要做DFT。也就是说，你交给foundry一个加法器的GDSII，他在做的过程和封装的时候都可能引入缺陷；拿到这个加法器芯片你怎么知道，里面的一个与门，厂家给你做的就是一个正常工作的与门呢？你怎么知道厂家做好的加法器的dier在封装之后引脚就能正常输入呢？一句话，就是通过DFT！如何做DFT呢，就是上面提到的拉。

USB Charger

Product advantages:
1. Stylish, portable, practical and convenient home charger
2. 6-port USB emergency charger, which can be used safely for tablet computers and can charge 6 devices at the same time
3. Built-in IC chip and fuse, protection: over current, over voltage, short circuit protection
4. The latest release, new design, beautiful appearance, high efficiency and energy saving, the best alternative to the original charger
5. Chargers for MP3, MP4, GPS, PDA, e-books, mobile phones, digital cameras, tablets, etc.

Features
(1) Overcharge protection
(2) Over discharge protection
(3) Short circuit protection
(4) Voltage stabilization protection.
(5) Automatic identification of mobile phone current protection.

1. Connect up to 6 USB devices at a time, and each device will receive a unique and tailor-made charge. The maximum output power of QC3.0 is 18W, which can optimize the charging of all devices.
2.2QC3.0+4 ports total 6 charging ports, which can charge 6 devices with a total power of 84W at the same time
3. With multiple protection safety systems, the product will automatically adjust the charging current according to the needs of the device being charged. Automatically detect and adjust the charging current to charge your device at the fastest speed.

One machine for multiple uses
The USB charger can charge 6 devices at the same time, and the smart recognition technology will detect and provide the best charging level for each of your devices.
The maximum output current of a single USB port is 2.4A. 2QC3.0 has 6 charging ports, which can charge 6 devices at the same time without causing shunting or reducing power. The USB charger can quickly charge your devices. Smartphones and tablets can receive up to 2.4 amps of current, so you can use the device as you like while charging.
Over-current, over-charge, and short-circuit protection will make charging safe, without any risk of overheating or damaging the device. Passed CE/FCC/ROSH/PSE/CCC certification. Through safety certification to ensure safe use.

Usb Charger,Usb C Charger,Usb C Power Adapter,Portable Usb Charger

Shenzhen Jinziming Electronic Technology Co.,LTD , https://www.powerchargerusb.com