Three co-simulation and benchmark analysis

Often, when designing large FPGA-based signal processing systems, designers often need time-consuming and labor-intensive simulations. The FPGA design tool, represented by Xilinx System Generator for DSP, solves this problem by providing a reliable hardware-in-the-loop interface that allows FPGA hardware to be placed directly into the design simulation.

By simulating partial designs on hardware, these interfaces can greatly increase the speed of simulation—usually by one or more orders of magnitude. Using hardware-in-the-loop also allows designers to debug and verify FPGA hardware in real time.

System Generator for DSP provides a hardware-in-the-loop interface for multiple types of FPGA development platforms. These platforms typically establish communication with PCs through different physical interfaces. For example, a JTAG co-simulation interface allows any FPGA board with a JTAG header and a Xilinx FPGA to be co-simulated within System Generator for DSP. Other types of boards, such as the XtremeDSPTM development kit, communicate over the PCI bus. Until recently, system co-simulation (such as video and image processing) with high memory bandwidth and throughput requirements was only available on development boards that communicate directly with PCs via PCI or PCMCIA interfaces.

System Generator for DSP 8.1 includes a new Ethernet co-simulation interface that enables the Xilinx ML402* evaluation platform to have high-bandwidth co-simulation capabilities for the first time. The ML402 development board will be remotely connected to the computer via a standard Ethernet cable or via a network.

At the heart of the interface is the Xilinx Tri-Mode Ethernet MAC core, which supports 10/100/1000 Mbps half-duplex and full-duplex modes of operation. When a designer creates a design using an Ethernet hardware co-simulation interface, System Generator for DSP automatically builds the necessary logic around the design to communicate with the FPGA over the Ethernet connection during the simulation (Figure 1). . You can also double-click on any of the designed System Generator modules to open its parameter configuration dialog to generate a design for Ethernet hardware co-simulation. Under the Compile menu, select ML402/Ethernet Compilation from the Hardware Co-Simulation menu (see Figure 2). You can choose between two different Ethernet co-simulation modes.

The network-based interface allows developers to co-simulate FPGA hardware connected to standard IPv4 networks. Since IPv4 is a ubiquitous network, network-based interfaces provide a convenient way to establish communication with remote FPGA development boards connected to wired or wireless networks. This interface manages communication details and error handling in the background (re-transmission after packet loss). System Generator for DSP determines which platform to communicate with during the co-simulation process by analyzing the IP address of the ML402 board (Figure 3).

The second mode of Ethernet co-simulation is a point-to-point interface that uses the original Ethernet frame to establish high-bandwidth communication with the ML402 board through the data link layer. Unlike the network-based mode, the point-to-point interface focuses on low-level communication on the local network segment. The co-simulated data is transmitted via a standard UTP Ethernet cable that connects the ML402 board to the computer. This means that your computer must have a free Ethernet jack to establish a connection.

The point-to-point interface can support the Gigabit Ethernet standard. If the interface is configured to use jumbo frames, the data transfer performance will be greatly improved. With this interface connection, you can even co-simulate over-bandwidth applications.

Both Ethernet co-simulation interfaces support a new device configuration method that supports the configuration of Ethernet using the Xilinx System A*M solution. This configuration process can be performed on the same Ethernet connection for co-simulation, thus eliminating the need for secondary programming cables such as Xilinx Parallel Cable IV or Platform. Cable USB. The ML402 development board also comes with a Compact Flash card that contains a special bootloader image that is automatically downloaded to the FPGA at power-up. The image can be reconfigured with a new FPGA co-simulated data bitstream that is transmitted over the Ethernet cable at the start of the simulation. The entire configuration process is controlled transparently by System Generator for DSP.

A 5&TImes;5 filter operator design model named conv5x5_video_ex is included in the System Generator for DSP 8.1 software tool. This design demonstrates that two-dimensional image filtering can be effectively implemented using an n-tap MAC FIR filter. Figure 4 shows the top-level design of System Generator for DSP.

In addition, the design includes a hardware co-simulation test platform that allows cyclic video sequences to flow through the 5&TImes;5 core at real-time frame rates. During each simulation cycle, video frames are transferred to the FPGA for processing. Once in the FPGA, each frame is filtered by the 5&TImes;5 core and then passed back to the computer for analysis using Simulink. During the simulation, two Simulink matrix indicator modules display unfiltered and filtered images, respectively. Figure 5 shows the data flow through the test platform.

The 5&TImes;5 filter design example was compiled to implement point-to-point Ethernet hardware co-simulation and co-simulated using the Xilinx ML402 development board. We compared the hardware simulation speed with the software simulation speed. The benchmark specifically considers the number of processed frames read back per second and compares the results to the software simulation time spent on filtering operations for a single frame.

Figure 6 summarizes the simulation acceleration achieved by Ethernet co-simulation compared to pure software simulation. The results show that the simulation speed is increased by about 50 to 1,000 times. In real-world designs, the speed increase depends on a number of factors, including the complexity of the design, the number of I/O ports, and the flow of I/O data. Figure 6 also shows that two other important factors related to Ethernet settings—link speed and the maximum frame size that can be tolerated—can also affect the performance of co-simulation.

As the link speed increases, we find that the time spent on simulation is greatly reduced because there is more bandwidth available for co-simulated data. In addition, if the jumbo frame support function of Gigabit Ethernet is enabled (to maximize the efficiency of burst data transmission and increase the maximum allowable frame size), the performance of co-simulation can be further improved.

System Generator for DSP's Ethernet hardware co-simulation interface provides a convenient and high-bandwidth solution for video and image processing application emulation on the Xilinx ML402 platform. This type of interface allows for the simulation of a remote FPGA platform, or for higher performance, to create conditions for simulations of development boards that are directly connected to the host via an Ethernet cable. With the System ACE solution, designers can complete device configuration over Ethernet, eliminating the need for secondary programming cables. As the benchmark results show, this interface can greatly increase the speed of simulation. The Xilinx System Generator for DSP v8.1 software tool includes an Ethernet co-simulation interface and a video processing reference design.

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